Recently, methods of integrating cells in a vertical direction with respect to a substrate have been developed to accomplish a high integration of semiconductor devices. To form the semiconductor devices including cells having a vertically integrated structure, a sacrificing layer and an insulating layer are laminated and then etched to form an opening portion. However, as the number of the laminated layers increases, a problem of lifting off of the layers are frequently generated. In addition, the formation of channel layer patterns of a vertical structure having uniform heights may be challenging.